What you’ll be doing:
Micro architecture design.
RTL (Verilog) coding.
Design implementation using Synopsys/Cadence tools.
Simulate, debug and write tests to verify design functionality and performance. (IP/SOC/FPGA/EMU design/verification direction)
Synthesis/Netlist quality check/Formal verification, Chip partitioning, Timing constraints development for various function/dft modes, Co-work with PR on floorplan and achieve timing closure, Timing sign off. (PD Direction)
Responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. (DFT Direction)
FPGA/EMU synthesis, partitioning and emulating using Synopsys/Cadence etc. Tools and FPGA/EMU ‘s infrastructure flow implementation (FPGA/ EMU direction)
Methodology in any of above areas.
What we need to see:
MS degree from EE/CS or related majors from a prestigious university.
Good knowledge in digital circuit design.
Experience in using Verilog HDL.
Experience in various of ASIC EDA tools.
Fluent in English reading and writing.
Self-motivated, good team player.
NVIDIA 是全球视觉计算技术的行业领袖及GPU的发明者。我们发明的 GPU 不仅重塑了计算机图形，而且还为计算开辟了新的轨道。自那之后， GPU 计算数度演进，不断推动高性能计算和人工智能领域的发展。这些技术反过来也在助力科学家、医生、创作者和工程师在世界各地推动积极变革。